TILE64
id:
tile64-307-17183405
title:
TILE64
text:
TILE64 is a VLIW ISA multicore processor manufactured by Tilera. It consists of a mesh network of 64 "tiles", where each tile houses a general purpose processor, cache, and a non-blocking router, which the tile uses to communicate with the other tiles on the processor. The short-pipeline, in-order, three-issue cores implement a MIPS-inspired VLIW instruction set. Each core has a register file and three functional units: two integer arithmetic logic units and a load–store unit. Each of the cores
brand slug:
wiki
category slug:
encyclopedia
description:
original url:
https://en.wikipedia.org/wiki/TILE64
date created:
date modified:
2024-02-03T20:38:12Z
main entity:
{"identifier":"Q3979563","url":"https://www.wikidata.org/entity/Q3979563"}
image:
{"content_url":"https://upload.wikimedia.org/wikipedia/commons/c/cc/Tile64-Tile.svg","width":319,"height":287}
fields total:
13
integrity:
14